In the race to store more data in smaller spaces, the industry has long focused on physical scaling—shrinking silicon, stacking layers, and packing more bits into memory cells. But as flash memory becomes denser, it also becomes more fragile. Then, as physical limits tighten, innovation has also shifted to something less visible: math.
Tricky bits
In Kfar Saba, a tree-lined Israeli suburban high-tech hub, Dr. Eran Sharon leads a team of technologists from around the globe. A Distinguished Engineer in Sandisk's R&D Engineering, Dr. Sharon has been pioneering advanced algorithms for over three decades.
"People are probably unaware of the complex algorithms and advanced math involved in every presumably simple operation of storing or reading data from their memory device," Dr. Sharon said.
While our always-connected world assumes the flawless flow of digital information, behind the scenes, things look very different. Because every time data moves—whether saved, read, or transmitted—it faces a spate of corrupting influences that jumble the original state of the 1s and 0s that make up our data.
Information theory, which emerged in the 1940s, laid the groundwork for fixing these bit errors with math. Just like a spell checker uses context and rules to correct typos, error correction codes rely on mathematical schemes to detect which bits got flipped and how to fix them.
"Error Correction Codes (ECC) work by adding redundant bits that describe attributes of the original data," Dr. Sharon said.
He explained that the most common approach is to add parity bits. Parity bits indicate whether the number of 1s within predefined subsets of the bits is odd or even. Adding a parity bit is done as part of an encoding process, before storing the data in the memory. And when reading from the memory, a decoding process is used to correct errors by flipping a minimal number of bits until all parity constraints are satisfied.
"The trick is to do this with a minimal amount of redundancy, as close as possible to information theoretic limits (aka the 'Shannon limit'), and with low complexity and power consumption," he concluded.
The pioneering bit
Dr. Sharon's team has spent the last decade building Sandisk's proprietary error-correction and Digital Signal Processing (DSP) engine, Sentinel ECC&DSP™. These algorithmic solutions are at the core of Sandisk's technology, powering everything from enterprise and client SSDs to embedded Flash, USB drives, and memory cards. Over the years, the team's innovations have earned more than 400 patents.
Yet nothing about Dr. Sharon's demeanor would give away that he's one of the world's leading experts in error correction coding and signal processing for storage, or that his groundbreaking algorithmic work helped pioneer the world's first Quad-Level Cell (QLC) NAND, shaping the course of Flash memory.
When Sandisk and Toshiba introduced the first commercial product based on Multi-Level Cell (MLC) technology in 2001, it marked a revolutionary shift in Flash memory design.
"By storing two bits of data in each cell, MLC doubled storage capacity and slashed the cost of NAND flash, making it the preferred storage solution for everything fast, small, and portable," Dr. Sharon said.
But the breakthrough begged the question of how far NAND scaling could really go.
Just a year later, M-systems (later acquired by Sandisk) teamed up with Tel Aviv University to explore a NAND Flash solution that could store four bits per cell.
The challenge wasn't just one of physics. Squeezing 16 voltage states into a narrow voltage window could only work by overlapping them, meaning that any margin for distinction would be lost. The level of precision needed to correct errors was considered impossible.
